This invention generally relates to the art of electrical connections and, particularly, to a contactless interconnecting system between a computer chip package and a circuit board.
As semiconductor devices become more complex, the interconnections between the silicon wafer or xe2x80x9cdiexe2x80x9d and appropriate circuit hardware continue to evolve and become more complex because of the difficulty of mechanical interconnections. This is due, in part, to the ever-increasing miniaturization and high density of electronic circuitry. Transmitted signals are becoming faster and faster (i.e., higher frequencies) and semi-conductor packages are becoming thinner and thinner (i.e., closely compacted). In some anticipated applications, it may be practically impossible to use conventional interconnecting systems, i.e., typical metal contacts or terminals.
Typical mechanical interconnecting systems incorporate conventional terminal pins and sockets or other male and female configurations or interengaging spring connections. With such traditional metal-to-metal interconnections, it is essential to provide a wiping action between the terminals or contacts to remove contaminants or oxidants. Unfortunately, miniaturized semi-conductor interconnections are so small that such traditional mechanical interconnecting systems are not possible. Even traditional solder connections are difficult if at all possible because of the extremely complex hard tooling required for use with miniaturized or closely spaced components of a semi-conductor interconnecting system. In some applications, it may be necessary to rely on electrical or magnetic field coupling as a possible alternative, and the present invention is directed to satisfying this need and solving the problems enumerated above.
An object, therefore, of the invention is to provide a new and improved contactless interconnecting system, particularly such a system between a computer chip package and a circuit board.
In the exemplary embodiment of the invention, the system includes a computer chip package having a silicon wafer or xe2x80x9cdiexe2x80x9d. A support structure mounts the wafer and includes a wall with a substantially planar upper surface and a substantially planar lower surface. The wall is fabricated of a material having a relatively high dielectric constant. A pattern of discrete terminal lands are provided on the upper surface of the wall and are electrically coupled to the silicon wafer. A circuit board is disposed below the wall of the computer chip package and includes a substantially planar upper surface having a pattern of discrete circuit pads aligned with the terminal lands.
As disclosed herein, the wall of the chip package comprises an exterior wall of a housing within which the silicon wafer is packaged. The wall may be fabricated of a material having a relatively high dielectric constant.
Other objects, features and advantages of the invention will be apparent from the following detailed description taken in connection with the accompanying drawings.